A compositional model for synchronous VLSI systems

technical reportCurrently available hardware specification languages have two serious deficiencies: (i) inadequate protocol definition capabilities; (ii) lack of a compositional model. We now explain these in more detail

Formal methods for surviving the jungle of heterogeneous parallelism

pre-printThe parallel programming community will soon be entering the ‘jungle' of heterogeneous hardware and software. Unfortunately, we are not adequately preparing future programmers (today's students) to cope with the many challenges of heterogeneous concurrency, especially in their ability to rigorously specify and verify concurrent systems. Concerted action is urgently needed to create a body of education material supplemented by effective software tools that help gain working knowledge of specification and verification techniques. We suggest funding models and incentives that can help create this material and put them into wide practice

HOP: A formal model for synchronous circuits using communicating fundamental mode symbolic automata

technical reportWe study synchronous digital circuits in an abstract setting. A circuit is viewed as a collection of modules connected through their boundary ports, where each port assumes a fixed direction (input or output) over one cycle of operation, and can change directions across cycles. No distinction is made between clock inputs and non-clock inputs. A cycle of operation consists of the application of a set of inputs followed by the stabilization of the module state before the next inputs are applied (i.e. fundamental mode operation is assumed). The states and inputs of a module are modeled symbolically, in a functional notation. This enables us to study not only finite-state controllers, but also large data paths, possibly with unbounded amounts of state. We present the abstract syntax for modules, well-formedness checks on the syntax, the formal semantics in terms of the denotation of a module, and the rule for composing two modules interconnected and operating in parallel, embodied in the operator par. It is shown that par preserves well-formedness, and denotes conjunction. These results are applicable to virtually every kind of synchronous circuit (e.g. VLSI circuits that employ single or multiphase clocks, circuits that employ switch or gate logic structures, circuits that employ uni- or bi-directional ports, etc.), thanks to the small number of assumptions upon which the HOP model is set up

Asynchronous circuit verification using trace theory and CCS

technical reportWe investigate asynchronous circuit verification using Dill's trace theory as well as Milner's CCS (as mechanized by the Concurrency Workbench). Trace theory is a formalism specifically designed for asynchronous circuit specification and verification. CCS is a general purpose calculus of communicating systems that is recently being applied for hardware specification and verification also. Although both formalisms are similar in many respects, we find that there are many interesting differences between them when applied to asynchronous circuit specification and verification. The purpose of this paper is to point out these differences, many of which are precautions for avoiding writing incorrect specifications. A long-term objective of this work is to find a way to take advantage of the strengths of both the Trace Theory verifier and the Concurrency Workbench in verifying asynchronous circuits

Some unusual micropipeline circuits

Journal ArticleWe present a few unusual Micropipelines (Sutherland, CACM, September 1989) that employ the Muller C-ELEMENT or an extension of the C-ELEMENT called LOCKC (Liebchen and Gopalakrishnan, ICCD, 1992). We first describe two variations of the two-dimensional Micropipeline structure realized using ordinary C-ELEMENTs. These micropipelines can be used to control wavefront arrays (S.-Y.Kung et.al, IEEE Computer, 1987). Next, we present a ring style arbiter realized using a LocKC-based one-dimensional micropipeline. Finally, we present a solution to the symmetric crossbar arbitration problem posed by Tamir and Chi (IEEE Trans. Parallel and Dist Systems, Jan '93) using a circuit that employs the two-dimensional micropipeline as well as the LOCKC. We present various circuits to solve the symmetric crossbar arbitration problem, including ones that consume very little power when idling

An integration of dynamic MPI formal verification within eclipse PTP

PosterOur research goals were to verify practical MPI programs for deadlocks, resource leaks, and assertion violations at the push of a button and be able to easily visualize the results. We also sought to integrate these capabilities with the Eclipse IDE via an Eclipse plug-in for the Parallel Tools Platform (PTP). We present here the result of our work, GEM - Graphical Explorer of MPI

Efficient symbolic simulation based verification using the parametric form of boolean expressions (rev.)

technical reportWe present several new techniques to make symbolic simulation based verification efficient. These techniques hinge on the use of the parametric form of a boolean expression (e.g. the parametric form for the boolean expression XQ V -<xi is the equivalent expression 3a b . (XQ = a V 6) A (xi = b), where a and b are the parameters). We illustrate several uses of the parametric form that reduce the number of symbolic simulation vectors as well as the time for symbolic simulation based verification. In the first technique, applicable to the verification of non-regular designs, minimally instantiated symbolic simulation vectors are first generated, and all these vectors are encoded into one vector using parametric variables. The second technique also pertains to non-regular designs, and offers a way to compactly encode input constraints using the parametric form during symbolic simulation. The third technique relates to the verification of regular arrays. It is shown that many regular arrays require input constraints to be obeyed, and that these constraints can be encoded using parametric variables. Experimental results are obtained using the COSMOS symbolic simulator, and are used to compare the relative merits of the various techniques. In all the examples considered, the use of the parametric form enhances the speed of the symbolic simulation process, mainly through a favorable tradeoff between the number of simulation vectors (which are very much reduced) and the average number of symbolic variables per vector (which go up only by a small amount)

Formalization and analysis of a solution to the PCI 2.1 bus transaction ordering problem: PVS files

Journal ArticleThe following PVS files are being put on our technical reports server and are available through anonymous FTP. Look for file "pci_pvs_files.tag.gz" in the TR directory

The 'test model-checking' approach to the verification of formal memory models of multiprocessors

technical reportWe offer a solution to the problem of verifying formal memory models of processors by com bining the strengths of model checking and a formal testing procedure for parallel machines We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety properties whose violations pinpoint the ordering rule being violated Our experimen tal results on Verilog models of a commercial split transaction bus demonstrates the ability of our method to e??ectively debug design models during early stages of their developmen